In semiconductor devices, it is well known to have thin film (on the order of about 500 μm or less) resistors embedded in the back-end-of-the-line (BEOL) of the chip through either a damascene approach or a subtractive etch method. The BEOL thin film resistors are preferred over other types of resistors because of lower parasitics. However, the sheet resistivity or the various resistors formed over the entire wafer may vary and go beyond specifications due to poor process control. In an advanced manufacturing line, wafers out of specification are often scrapped for quality control.
The resistor is one of the most common electrical components used in almost every electrical device. Conventionally, doped polysilicon is used as the material of a resistor. However, the conventional resistor can only provide a limited resistance within a limited dimension as the device feature size shrinks. For overcoming this problem, new materials with higher resistivity and new integration schemes are required for fabrication of thin film resistors in a highly integrated semiconductor device.
Resistive thin films such as CrSi and TaN are often used as resistors in semiconductor devices. Integration schemes used to fabricate the resistor components within the interconnect structure falls into two primarily categories.
In a first integration scheme, which is disclosed, for example, in U.S. Pat. No. 6,207,560, a thin film resistor is formed by etching on top of an insulator. A metallic layer is then deposited on top of the resistive layer and is used to protect the resistive layer from being damaged during the sequential etching process. After the resistor has been defined, the underlying dielectric is patterned and etched to define the interconnect pattern. Finally, a metallic layer for the interconnect is deposited, patterned, and etched. Although the protective layer is capable of protecting the resistive layer, the protection is limited and the resistive layer may be damaged during the etching process.
In a second integration scheme, a thin film resistor is formed by etching on top of an insulator. An interlevel dielectric is then deposited, followed by patterning and etching processes to define an upper level interconnect structure with vias connected to the underlying thin film resistor. A planization process is typically required after deposition of the interlevel dielectric material in order to compromise any possible topography related issues caused by the underlying resistors.
U.S. Patent Application Publication No. 2004/0027234 discloses a resistor including upper surface electrodes formed on a main surface of a substrate and side face electrodes disposed on side faces of the substrate and connected electrically to the pair of upper surfaces electrodes, respectively.
U.S. Pat. No. 6,232,042 discloses a method for fabricating an integral thin film metal resistor that generally entails applying a photosensitive dielectric to a substrate to form a layer. The dielectric layer is photoimaged to polymerize a first portion of the dielectric layer on the first region of the substrate, leaving the reminder of the dielectric layer unpolymerized. An electrically resistive film is then applied to the dielectric layer, and the dielectric layer is developed to remove concurrently the unpolymerized portion thereof and the portion of the resistive film overlaying the unpolymerized portion, so that a portion of the resistive film remains over the second portion to form the resistor.
U.S. Pat. No. 6,083,785 discloses a method of fabricating a semiconductor device having a resistor film. This prior art method includes forming an isolation region in a part of a P-well of a semiconductor substrate. A resistor film as a first conductor member is formed on the isolation region. By utilizing a salicide process, a resistor can be formed without lowing the resistance of the resistor film.
U.S. Pat. No. 5,485,138 discloses an inverted thin film resistor structure comprising a metallic interconnect layer having predetermined patterns delineating two or more metallic leads overlaying a supporting insulator, an interlevel dielectric layer, and planarized so as to expose a top contact portion of the metallic interconnect leads, and an inverted thin film resistor overlaying a portion of the planarized interlevel dielectric layer and overlaying the exposed top contact portions of the interconnect leads.
Prior art resistors can be trimmed by using laser or high-energy particle beam. But, these processes are not clean and therefore have never become a common practice. Resistor can also be programmed by using a shut transistor to deselect at least a portion of the resistor from a chain of the resistor circuit. Such a programming method has two problems, the resolution of the programming is limited by the LSB (least significant bit) device size, and the shut device itself has some resistance. Tuning precision is thus poor.
In view of the above, there is still a need for providing interconnect structures having at least one thin film resistor that is located at the same interconnect level as a neighboring conductive interconnect as well as a method of fabricating such an interconnect structure. The term “conductive interconnect” is used in the present application to denote either a conductive line or conductive via/line combination.